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![PDF] Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/0ae61a5712d8ed9a1b249310f56d0e170143e3f0/3-Figure4-1.png "PDF] Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS | Semantic Scholar")
PDF] Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS | Semantic Scholar
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